Circuits and Methods to harvest energy from transient on-chip data

ABSTRACT

Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1→0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0→1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

PROVISIONAL PATENT APPLICATIONS FILED

63/090,169 & 63/139,744

FIELD OF INVENTION

The present invention relates to harvest of electrostatic energy from transient on-chip data to improve the energy efficiency of digital CMOS circuit operation.

BACKGROUND OF INVENTION

In recent years, deep neural networks (DNNs) have become the solution for many AI applications including computer vision, speech recognition and robotics implementing machine learning methods. While these neural networks deliver sufficient accuracy—it comes at the cost of high computational complexity with associated power drain limiting deep learning from being deployed on mobile devices with limited energy budgets. Smart phones for example, cannot run object classification with AlexNet in real-time for more than an hour [1]. Network issues of latency, bandwidth and availability could require battery/ambient powered IoT devices on the edge to not only sense and act without communicating to the cloud but also to take on more computationally intense tasks of learning or training a neural network. Neural networks for a myriad of IoT devices [2]can easily result in model sizes that are enormous—becoming computationally burdensome to their energy resources, demanding energy budgets that exceed provisions from batteries and conventional energy harvesting methods. Even where power is abundantly available as in a data center supporting AI workloads, where GPU accelerators consume as much as 400 W [3], the cost of electricity and the performance limits imposed by heat removal efficiency can be improved by lowering the switching (or Dynamic) energy consumption of digital CMOS circuits

PRIOR ART

In many applications requiring high speed CMOS circuit operation, precharged dynamic circuit techniques are preferred. These circuits are typically operated by pre-charging output nodes to the supply voltage during a pre-charge phase every clock cycle and conditionally discharging some of them, depending on the inputs during the evaluation phase. These techniques are energy inefficient since all of the charge discarded to the reference ground potential during evaluate must be resupplied during the precharge phase of the next clock cycle. High peak currents can also cause large di/dt noise causing voltage bumps in power rails with associated risks to signal integrity and reliability in high performance CMOS components.

Dynamic logic circuits that recycle some of the charge were proposed to improve the energy efficiency of circuit operation [4-6]. These circuit techniques precharge complementary outputs to half V_(DD) by charge sharing from the previous evaluation state, enabling a maximum of a 50% reduction in energy. Such schemes are relevant only when complementary signal pairs are used in implementing complex logic functions. Also, much of the charge recycle benefits are lost with performance degraded as well due to (i) high overheads in device count (ii) requirement of using complementary inputs and as many as 2-3 clock and enable inputs to each logic gate with their associated additional routing, performance and power overheads (iii) use of cross-coupled inverters as output drivers which increase the uncertainty of gate metrics in the presence of parameter variations and the offsets they develop, and (iv) with only a half-VDD gate-source voltage precharged to output and input nodes of output drivers for charge recycle operation, gate overdrive is degraded during evaluation phase. In one comparison [4]with static CMOS implementing full adders, the power-delay product of a full adder increases total energy nearly 10% over static CMOS. Moreover, neural network energy consumption is dominated by movement of data across the memory hierarchy [7-8]and the chip and not by dissipation from computation.

On-chip small voltage swing signaling schemes [9]have attempted charge recycling by stacking components (such as logic and clocking circuits) with predictable data switching activities in two adjacent voltage domains using simple push-pull regulators to balance current between the two domains to maintain the voltage at their interface. This approach could deliver a maximum of a quadratic reduction in power. Inefficiency introduced by voltage regulation is eliminated if the current between domains is matched. An approach to stack voltage domains without requiring regulators between them has been reported [10]using a balanced charge recycling bus where differing data activity between two links is compensated by swapping data between them periodically so that switching activity along the bus is exactly matched. These schemes however, are difficult to implement and also require circuits in the domains to be powered by reduced operating voltages.

Charge recycling techniques have been reported where the flow of electric charge from the supply rail (V_(DD)) to Ground is traced through more than one circuit/use through multiple voltage domains [11]. However, there is no energy advantage from recycling the charge through multiple voltage domains since it costs as much in energy to raise charge to the highest voltage domain as it does to do so cumulatively each of the stacked domains operating independently. The energy advantage of stacking voltage domains is only in removing the inefficiencies of on-chip voltage regulation from V_(DD) to much lower voltages that these domains would be powered with to benefit from quadratic reductions in their switching power. If the current between domains is not matched, the energy overhead consumed by regulators attempting to maintain domain interface at a fixed voltage, could diminish the quadratic energy improvements from operating each domain at reduced voltages.

Non-resonant approaches to returning/recycling stored energy on load capacitance include use of an inductor to discharge load capacitor of a clock network to the power grid instead of it being discharged to ground [12]. However, overheads of inductors, decoupling capacitors, integration with clock gating (and its accompanying overheads), and limited application to large clock load capacitances (as seen in a clock mesh) are challenges seen with this approach making it impractical and difficult to implement.

Smaller voltage transitions for each logic operation using ‘recycled charge’also come with the disadvantages of smaller margins and lower performance. In multiple instances, these make implementations impractical. For e.g., in [13-14], a smaller (than V_(DD)) voltage is applied across a BL pair during an SRAM Write operation to enable lower energy dissipation per Write operation. By sharing/recycling charge across a set of BL pairs, Writes are attempted with smaller voltage swings on the BL (instead of full rail-rail BL swings during a conventional SRAM Write). For small geometry devices it becomes harder to write [15]to the bitcell even with the full supply voltage across a bit line pair—due to increasing electrical variability seen in small-geometry bitcell transistors. Circuit overheads introduced by full CMOS transmission gates to move charge between columns comes at a significant cost in area, control and performance.

Adiabatic switching in reversible logic circuits moves charge from the power supply to a load capacitance using slow constant current charging without energy dissipation [16-17]. It enables the recycling of energy to reduce the total energy drawn from the power supply by reversing the current source using non-standard AC or pulsed power supplies with time varying voltage or current. In sharp contrast to conventional CMOS circuit operation, charge and energy are not discarded after being used only once—with pulsed/sinusoidal power supplies designed to be able to retrieve the energy fed back to it. The problem areas limiting realization of practical low-power operation of CMOS chips using adiabatic or reversible logic techniques: (1) the energy-efficient design of the combined power supply and clock generator (2) logical overhead needed to support reversible logic functions [16]and (3) the alternative of scaling operating voltages with feature size and improving performance—that comes with conceptual simplicity and high payback of lower power dissipation, has been preferred by industry.

SUMMARY OF INVENTION

Conventional CMOS operation as illustrated by an inverter driving a capacitive load C and which draws energy equal to CV_(DD) ₂ from the power supply rail at voltage V_(DD) during a 0→1 transition at its output, of which energy equal to (½)CV_(DD) ₂ is stored at the output. A 1→0 transition at the output discharges all of this stored energy to the reference ground potential of the inverter at voltage Vss=0V.

In the proposed invention, an inverter driving the same capacitive load C as the above conventional CMOS inverter, draws energy equal to CV_(DD) ₂ —as a conventional CMOS inverter would, but a 1→0 transition at its output node harvests a fraction a of the charge held, at the output to a common grid/node raising its electric potential (where α is a positive fraction <1). Typical values of α are 0.25-0.4

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic illustrating conventional CMOS circuit schematic of an inverter and its operation in response to 1→0 and 0→1 input transitions

FIG. 2 is a circuit simulation of the conventional CMOS inverter circuit that shows voltage waveforms at the input and at the output terminals of the inverter in response to 1→0 and 0→1 input transitions. The Figure also shows the current waveform that illustrates current flow dependence on time for the 0→1 transition at the output and the 1→0 transition at the output

FIG. 3 is a schematic illustrating the proposed circuit of an inverter that harvests charge from its output at VDD to a common grid/node capacitance when the output makes a 1→0 logic transition moving 0.4x−0.25x of the charge held at its output at VDD to the harvest grid/node V2.

FIG. 4 is a circuit simulation of the proposed inverter circuit that harvests charge during a 1→0 logic transition at its output—showing voltage waveforms at the input and output terminals (that are practically identical to those observed in a conventional CMOS inverter (FIG. 2)) and current waveforms corresponding to current drawn from the power rail at voltage of VDD and current to the common grid/node V2 at voltage VDD/2

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 is a schematic illustrating operation of a conventional CMOS inverter 100 driving output node OUT 102 with a capacitive load C_(out) 104. The power rail 106 at electric potential V_(DD) provides total energy equal to C_(out)V_(DD) ₂ (derived in equation (1) below) during a 0→1 transition 108 at the output node OUT 102, storing energy of (½)C_(out)V_(DD) ₂ on the capacitor 104 at the output 102 modeled by equation (2) below. A 1→0 112 transition at the output 102 discharges from C_(out) 104 all of this stored energy on the capacitor C_(out) 104 at the output 102 to the reference ground node 110 at electric potential V_(SS)=0V

-   -   Energy drawn from VDD supply (during 0→1 transition at output)

∫I _(VDD)(t)V _(DD) dt=∫ _(VSS) ^(VDD) C _(out) V _(DD)dV_(out) =C _(out) V _(DD) ²   (1)

-   -   Energy stored at output

∫I _(VDD)(t)V _(out)(t)dt=∫ _(VSS) ^(VDD) C _(out) V _(out) dV _(out)=½C _(out) V _(DD) ²   (2)

-   -   Energy discharged from output (during 1→0 transition at output)

∫I _(VSS)(t)V _(out)(t)dt=∫ _(VDD) ^(VSS) C _(out) V _(out) dV _(out)=½C _(out) V _(DD) ²   (3)

FIG. 2 200 is an illustration of the time dependent voltage waveforms of the output node OUT (102 in FIG. 1 100) shown as the waveform V_(OUT) 202 in FIG. 2. The voltage waveform driving the input of the inverter 118 in FIG. 1, is shown in FIG. 2 as V_(IN) 204

The waveform of current flow 206 into the inverter from the power rail at voltage V_(DD) (106 in FIG. 1) is shown along the same x-axis of time (as used to plot voltage waveforms) in FIG. 2. The absolute value of the integral of the current waveform 206 over time in FIG. 2 200 equals the total charge Q drained from the power rail (106 in FIG. 1) to drive the output node 102 from 0→1. The energy consumed from the power rail 106 to accomplish this logic transition at the output node 102 equals [Q⋅V_(DD)]=C_(out)V_(DD) ₂ modeled in equation (1) above.

In FIG. 3 the proposed circuit schematic functioning as an inverter 300 shows parts highlighted in blue: a 2-input NAND 302 and a delay element 304 that also inverts its input. These highlighted parts have devices with much smaller widths (˜⅕ of driver transistors) than the other transistors (326,314,320) shown in black in this schematic 300.

The NAND gate 302 in this schematic generates an active low pulse at its output node 306 whose leading edge is triggered by a 0→1 transition at the input 308 and whose trailing edge is triggered by a 1→0 transition at the output node 310 loaded with a total capacitance C_(out) 312.

The leading edge of this active low pulse turns on PFET P2 314 which drives charge from the output node at logic ‘1’ and voltage VDD to be harvested on the common grid/node V2 316 (typically at a voltage between VSS and VDD and preferably at a voltage comparable to or lower than the logic threshold of the NAND gate 302).

The leading edge of the active low pulse at the output of the NAND gate 306, when delayed and inverted to drive the gate input 318 of NFET N1 326, turns on NFET N1 326 to begin discharging the output 310 to VSS—as the output voltage at node OUT 310 approaches V2. Note that a design requirement on the logic threshold voltage of the NAND gate 302 is that it is higher than the typical voltage node V2 would be raised to with harvested charge or during a dynamic equilibrium when rate of charge transfer to and from the common grid/node are balanced. Thus, node OUT 310 when being discharged to V2 through PFET P2 314, can trip the NAND 302 to produce the trailing low→high transition of the active low pulse at output of the NAND gate 306 to turn-off P2 314.

The NAND 302 would also trip when the N channel FET N1 326 begins conducting after the delayed and inverted leading edge of the active low pulse output from the NAND is inverted by the inverter 304 whose output turns on N1 326.

The output continues being discharged toward VSS—the reference ground terminal 324 as N1 320 is turned on. The trailing edge of the active high pulse driving the gate input terminal of the N channel FET, N1 326 turns this FET, N1 320 off. A small geometry keeper HVT NFET 328 holds the output to VSS. Its gate input is driven by the inverter input 308 with its source terminal connected to the reference ground voltage rail 322 at voltage VSS=0V and its drain terminal connected to OUT 310.

The trailing edge of the active low pulse at the output of the NAND 306 is triggered by the transition at the output node from VDD toward V2 since the logic threshold of the NAND 302 is higher than the voltage at which node V2 316 is typically charged to with harvested charge. The trailing edge is triggered by this feedback from OUT 310 to the input of the NAND 306.

The proposed circuit (1) maintains rail-rail operation (2) drives practically the same waveforms at its output as a conventional inverter and (3) while harvesting about 25%-40% of the total charge it discharges from its output 310—to the harvest grid node V2 316, instead of discharging all of that charge to the reference ground supply rail 322. The primary overhead in area is consumed by the PFET P2 in FIG. 3. The gates highlighted in blue in

FIG. 3 are small and can be replaced by equivalent standard cells. Transistors N1 320, P1 326 in FIG. 3 are identical to the transistors 116 and 114 in the schematic of the inverter in FIG. 100.

The NAND gate 302 and the delay element 304 can be optimized to maximize the energy harvested at the grid/node from the output node of the inverter—according to what voltage the harvested charge is typically held at when using the proposed inverter. The closer the voltage of the harvested charge at V2 316 is to VDD, the higher the optimal logic threshold voltage of the NAND gate 302 should be (to avoid reverse flow of current from harvest grid node to output node of inverter) and the shorter the delay value of the delay element 304 needs to be to minimize the delay overheads to accomplish the same 1→0 transition at the output of the inverter. This optimization is especially useful when operating at low, near threshold voltages

FIG. 4 400 is an illustration of the time dependent voltage waveforms of the output node OUT (310 in FIG. 3) shown as V_(OUT) 402 in FIG. 4. The input waveform driving the input 308 of the inverter in FIG. 3, V_(IN) 404 is also shown in FIG. 4

The waveform of current flow 406 into the inverter from the VDD power rail (324 in FIG. 3) is shown along the same x-axis (as used to plot voltage waveforms) in FIG. 4. The absolute value of the integral of this current 406 over time in FIG. 4 400 equals the total charge drained from the power rail (324 in FIG. 3) to drive the output from 0→1. Note that this charge is the same as drained by a conventional CMOS inverter shown in FIG. 2. The total charge transferred to the common grid/node V2 316 in FIG. 3 is the total area under the curve 408 in FIG. 4.

Note that the voltage waveform at the output node 310 in FIG. 3 is practically the same as the voltage waveform 202 of the output node (102 in schematic shown in FIG. 1) in FIG. 2 of a conventional inverter. In the schematic in FIG. 3 300 the total charge harvested from the output node 310 during a 140 transition to the common grid/node V2 316 is 25%-40% of the total charge drained from the power rail 324 in FIG. 3. Total current in the comparison is based on simulation of the entire circuit shown in FIG. 1 100 and FIG. 3 300—and thus includes parasitic contributions of all transistors to circuit operation. All parasitic capacitances of transistors and local wires in the complete schematic contribute to slew rate seen at the output and overheads incurred in propagation delay.

Switching energy consumption by logic gates with low fanouts (<4) are typically small. Gates driving a high fanout (>10) and/or long wires consume more energy and are best candidates for the proposed scheme that harvests charge from these large loads as they are discharged.

The transistor count increases in the proposed schematic shown in FIG. 3 300 compared to the 2 transistors used in a conventional CMOS inverter. However, area consumed by the proposed schematics in FIG. 3 300 does not increase proportionally with the number of transistors because the transistors of gates highlighted in blue (302, 304 in FIG. 3) are ˜5× smaller than any of the transistors drawn in black (326, 314 and 320 in FIG. 3 300). This because the load seen by the NAND gate 302 highlighted in blue is small—essentially lust the gate input of a single PFET (P2 314 in FIG. 3)—with the load from the delay element 304 much smaller. The transistors P1 320, N1 326 and P2 314 in FIG. 3 are comparable (in dimensions) to the transistors P1 114 and Ni 116 in a conventional CMOS inverter shown in FIG. 1 100 that drives the same capacitive load C_(OUT) 104 in FIG. 1 and 312 in FIG. 3. The gate footprint of the proposed schematic 300 (in FIG. 3) is not expected to be larger than 1.7×-2.0× of the CMOS inverter it replaces. Note that the proposed schematics are preferred as replacement candidates of CMOS inverters only when driving large loads—that offer the opportunity for larger energy reductions.

Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.

REFERENCES

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What is claimed is:
 1. An inverter harvesting charge from its output node comprising of N and P channel FETS with their drain terminals shorted together at the output terminal of the inverter. The source terminals of the N and P channel FETs are connected to the reference Ground and Power supply rails respectively. a second P channel FET whose source and drain terminals couple the output terminal of the inverter with a grid/node whose capacitance holds harvested charge at a voltage lower than the Power supply rail voltage. an input terminal and an output terminal of the inverter whose electric potentials makes full-swing transitions between the power rail voltage and the reference ground rail voltage. The input terminal of the inverter connected directly to the gate input terminal of the first P channel FET. a small HVT keeper N channel FET whose gate input terminal is driven by the input terminal of the inverter and whose source and drain terminals are connected to the reference ground rail at voltage VSS=0V and the output terminal of the inverter respectively. a 2-input NAND gate with its inputs driven by the input and output terminals of the inverter. The 2-input NAND gate output drives the gate input terminal of the second P channel FET and the input terminal of a delay element whose inverted output drives the N channel FET of the inverter
 2. The device as recited in claim 1 wherein the second P channel FET is enabled to move charge to the grid/node holding harvested charge from the output terminal of the inverter following a 0→1 logic transition at the input terminal of the inverter with this charge transfer self-disabled by a decreasing inverter output voltage that sets the output of the NAND gate to the power supply voltage as the inverter output voltage decreases below the logic threshold voltage of the NAND gate.
 3. The device as recited in claims 1,2 wherein the decreasing inverter output voltage is reinforced by the N channel FET of the inverter when the delayed, leading-edge 0→1 transition at the gate input terminal of the inverter N channel FET completes the 1→0 transition at the output of the inverter while transferring charge from the output of the inverter to the reference ground rail at voltage VSS=0V.
 4. The NAND gate is designed to have a logic threshold such that the voltage V2 at which harvested charge is held is lower than the logic threshold of the NAND gate. The delay element is designed to have a delay that is comparable to the time it takes for the output to decrease from voltage power supply rail voltage=VDD to a voltage comparable to the logic threshold of the NAND. 